Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that can be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream can be read from an external memory, conventionally an external integrated circuit memory such as EEPROM, EPROM, PROM, or the like, though other types of memory may be used. The collective states of the individual configuration memory cells then determine the function of the FPGA. In some cases, the designs implemented on an FPGA can be organized into modules, each module comprising a related group of programmable resources (e.g., CLBs, IOBs, and interconnect structure).
As feature size within an FPGA becomes smaller, especially for dense routing in sub-quarter-micron fabricated integrated circuits, globally synchronous communication at high clock frequencies over long-haul routing within an FPGA (such as FPGA internal module-to-module routing) is becoming more problematic. This difficulty is due at least in part to an increase in resistance-capacitance (RC) time constants. In some instances, none of the available paths of the interconnect structure from a source circuit to a sink circuit has a signal delay that is compatible with the desired clock period. That is, as clock frequencies increase, and delays in the interconnect structure also increase, a signal may not be able to propagate from one circuit to another within a target number of clock cycle(s). Thus, completely synchronous designs can become impractical, or even impossible.
Therefore, there exists a need in the art for point-to-point communication between respective portions of a programmable logic device integrated circuit, such as an FPGA, that facilitates module-to-module communication for an integrated circuit.
Additionally, it is desirable to facilitate communication over an interconnect structure with less delay to allow for “dynamic” or “on-the-fly” module configuration. Heretofore, at an interface, buffers were tri-stated to electrically isolate a module from one or more other modules while the isolated module was undergoing removal, initial or subsequent programming of programmable logic, or was not in use. This allowed such other modules to continue to operate, while taking a module undergoing configuration off-line.